Mid/Senior ASIC/FPGA Verification Engineer #1302

Overview

RAD is seeking a Mid/Senior ASIC/FPGA Verification Engineer to join our team developing advanced telecommunications ASIC/FPGA products.
In this role, you will create sophisticated verification environments using SystemVerilog/UVM and/or Specman methodologies to validate complex ASIC/FPGA designs.

Responsibilities

• Develop comprehensive verification plans and testbenches for complex telecom ASIC/FPGA designs.
• Implement and maintain verification environments using SystemVerilog/UVM and/or Specman methodologies, including the integration of verification IP.
• Create and execute constrained-random and directed tests to achieve high functional coverage and meet design specifications.
• Debug failing test cases and collaborate closely with design engineers to identify root causes and verify fixes.
• Analyze coverage metrics and refine test scenarios to ensure thorough verification of all features.
• Promote effective verification strategies, contributing to the continuous improvement of verification processes and methodologies.

Requirements

• Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field.
• 5+ years of hands-on experience in ASIC/FPGA verification.
• Strong proficiency in SystemVerilog/UVM and/or Specman methodologies.
• Participation in a few chip design and verification cycles
• Experience with coverage-driven verification, constrained-random testing, and assertion-based verification techniques.
• Proficiency with scripting languages (e.g., Python, Bash, csh) for automation in verification environments.
• Experience working on Linux systems.
• Excellent problem-solving skills and effective communication within a collaborative team environment.

Preferred Qualifications

• Hands-on experience in ASIC/FPGA design; knowledge of synthesizable Verilog is a significant advantage.
• Familiarity with telecom protocols and standards (e.g., Ethernet, timing synchronization protocols) and understanding of telecom applications.
• Experience with hardware-based validation platforms or FPGA prototyping (e.g., ASIC emulation on FPGAs, co-simulation) or QA testing in silicon projects.
• Experience with AI-based verification methods.
• Experience with board design/bring-up, digital synthesis, static timing analysis, place-and-route, or firmware/software development for chips.
• Experience managing Linux systems.
• Experience mentoring junior engineers or leading verification projects is a plus.
• Knowledge of quantum computing is not required, but the Verification Manager will appreciate it.