Experienced Verification Team Leader in RAD’s FPGA/ASIC R&D Group
The FPGA/ASIC group is responsible for the next generation of network interface devices at a new level of complexity, as well as for developing advanced products for our customers.
Roles and Responsibilities:
Opportunity to participate in the development of RAD’s next generation product line, and to know some of the leading technologies in the field of communications (network processors).
Participation in all stages of development, from verification programs and strategies, through the definition and implementation of complex verification environments.
Requirements:
Bachelor's degree in Computer Science/Electrical Engineering - mandatory
5 years of experience in defining and implementing verification environments in Specman/eRM or SystemVerilog/UVM environments
Good communication skills and teamwork - mandatory
Proven experience in a managerial position - advantage
Experience with scripts (Python or Bash), SOC environments, formal verification, Palladium, gate level simulations - advantage