TDM Timing over PSN

This paper presents a brief overview of the theory and practice of timing in pure TDM and TDMoIP networks.

TDM signals are isochronous, meaning that the time between two consecutive bits is theoretically always the same. This time is called the unit interval (UI); for T1 signals the UI is defined to be 647 nanoseconds, and for E1 the standards dictate 488 nanoseconds. In order to maintain isochronicity and to remain within tolerances specified by recognized standards, a TDM source must employ a highly stable and accurate clock.

The stringent clock requirements are not capriciously dictated by standard bodies; rather, they are critical to the proper functioning of a high-speed TDM network. Consider a TDM receiver utilizing its own clock when converting the physical signal back into a bit-stream. If the receive clock runs at precisely the same rate as the source clock, then the receiver need only determine the optimal sampling phase. However, with any mismatch of clock rates, no matter how small, bit slips will eventually occur. For example, if the receive clock is slower than the source clock by one part per million (ppm), then the receiver will output 999,999 bits for every 1,000,000 bits sent, thus deleting one bit. Similarly, if the receive clock is faster than the source clock by one part per billion (ppb), the receiver will insert a spurious bit every billion bits. One bit slip every million bits may seem acceptable at first glance, but translates to a catastrophic two errors per second for a 2 Mbps E1 signal. ITU-T recommendations permit a few bit slips per day for a low-rate 64 kbps channel, but strive to prohibit bit slips entirely for higher-rate TDM signals.

Temperature changes, imperfections in materials, aging, and external influences will inevitably affect a clock’s rate, whether that clock is atomic, quartz crystal, or pendulum based. Hence no clock will remain at precisely the same rate forever, and no two physical clocks will run at exactly the same rate for extended periods of time. In order to eliminate bit slips, we must ensure both that the long-term average UI of source and receive clocks are identical (any rate difference, no matter how small, will eventually accumulate up to a bit slip), and that its short-term deviations from the average are appropriately bounded.

The variation of a clock’s rate over time is conventionally divided into two components, jitter and wander. Wander expresses slow, smooth drifting of clock rate due to temperature changes, aging and slaving inaccuracies; while jitter conveys fast, erratic jumps in UI caused by phase noise phenomena and bit-stuffing mechanisms. The border between the two components is conventionally set at 10 Hz. In order to eliminate bit slips, the standards impose strict limits on tolerable jitter and wander of TDM clocks.

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